High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. One way of achieving high data reliability is by introducing fuse arrays including a plurality of fuse sets and a plurality of redundancy decoders corresponding to the plurality of fuse sets to provide substitute rows/columns of memory cells for defective rows/columns of cells in a memory array. The addresses for defective memory of the array may be mapped to redundant memory, thereby repairing the memory location for the address. Each fuse set may store an address of a defective cell (Defective Address). Each redundant address decoder receives row/column address signals and compares the received row/column address signals to the defective addresses stored in the fuses. If the received row/column address signals correspond with a defective address stored in any fuse, access to the received row/column address is disabled and the redundant row/column address may be accessed instead. Defective addresses may be obtained by a plurality of tests that may be performed during manufacture of the semiconductor memory.
As the density of memory has increased for semiconductor memory, additional redundant memory is needed to maintain yield of fully functioning memories. The additional redundant memory requires larger fuse arrays with a greater number of fuses to store potentially more addresses. The larger the fuse array, the more area is consumed on a semiconductor die by the fuse arrays and associated programming logic, high current and high power bussing, and fuse addressing circuity. Therefore, there is a desire for reducing the size of the fuse array and the associated circuits while maintaining the repairability of larger memory density semiconductor memory.